The present invention relates to a semiconductor device, and more particularly, to a semiconductor memory device and a method for generating an internal control signal, capable of being fast driven with low power consumption.
Unlike a general dynamic random access memory (DRAM), a DRAM for a mobile device has given priority to power consumption rather than a driving speed. The DRAM for the mobile device will be referred to as a mobile DRAM. However, in recently years, the driving speed is also regarded as a very important factor. Input blocks for generating an internal control signal in the typical DRAM and the mobile DRAM will be described below.
FIG. 1 is a block diagram of an internal command generating circuit in a typical synchronous DRAM (SDRAM).
Referring to FIG. 1, the typical SDRAM includes first to third address buffers 12, first to third address latches 14, an address decoder 16, an address command combiner 18, first to fourth command buffers 22, first to fourth command latches 24 and a command decoder 26.
The first to third address buffers 12 receive addresses ADD1, ADD2 and ADD3, respectively. The first to third address latches 14 latch output signals of the first to third address buffers 12 and output internal addresses INT_ADD1, INT_ADD2 and INT_ADD3 in response to an internal clock CLK, respectively. The address decoder 16 decodes the internal addresses INT_ADD1, INT_ADD2 and INT_ADD3 to output a plurality of address information signals ADD_INFO<0:N>, N being a positive integer. The first to fourth command buffers 22 receive external commands /RAS, /CAS, /WE and /CS, respectively. The first to fourth command latches 24 latch output signals of the command buffers 22 and output internal commands /RAS_1, /CAS_1, /WE_1 and /CS_1 in response to the internal clock CLK, respectively. The command decoder 26 decodes the internal commands /RAS_1, /CAS_1, /WE_1 and /CS_1 to output pre-control signals PRE_ACT, PRE_WT, PRE_RD and PRE_MRS in response to the internal clock CLK. The address command combiner 18 combines output addresses of the address decoder 16 and the pre-control signals PRE_ACT, PRE_WT, PRE_RD and PRE_MRS to output a plurality of internal driving control signals INT_ACT<0:7>, INT_WT<0:7>, INT_RD<0:7> and MRS having address information.
Since the respective buffers and the respective latches are implemented with the same circuit configuration and are driven in the same manner, the reference numerals are assigned to only one buffer and one latch.
A method for driving the internal command generating circuit illustrated in FIG. 1 will be described below.
First, the external commands /RAS, /CAS, /WE and /CS and the addresses ADD1, ADD2 and ADD3 are inputted.
The first to third address buffers 12 receive the addresses ADD1, ADD2 and ADD3 and convert them into internal voltage levels, and the first to third address latches 14 latch output signals of the address buffers 12 and output the internal addresses INT_ADD1, INT_ADD2 and INT_ADD3 when the internal clock CLK has a logic low level. The address decoder 16 decodes the internal addresses INT_ADD1, INT_ADD2 and INT_ADD3 to output the plurality of address information signals ADD_INFO<0:N>.
The first to fourth command buffers 22 receive the external commands /RAS, /CAS, /WE and /CS and convert them into internal voltage levels, respectively. The first to fourth command latches 24 latch the output signals of the command buffers 22 and output the internal commands /RAS_1, /CAS_1, /WE_1 and /CS_1 when the internal clock CLK has a logic low level. The command decoder 26 decodes the internal commands /RAS_1, /CAS_1, /WE_1 and /CS_1 to output the plurality of pre-control signals PRE_ACT, PRE_WT, PRE_RD and PRE_MRS in response to the internal clock CLK of a logic high level.
The address command combiner 18 combines the pre-control signals PRE_ACT, PRE_WT, PRE_RD and PRE_MRS and the address information signals ADD_INFO<0:N> to output the internal driving control signals INT_ACT<0:7>, INT_WT<0:7>, INT_RD<0:7> and MRS. The internal driving control signals INT_ACT<0:7>, INT_WT<0:7>, INT_RD<0:7> and MRS are outputted in response to the internal clock CLK of a logic high level.
As described above, the internal driving control signals INT_ACT<0:7>, INT_WT<0:7>, INT_RD<0:7> and MRS are produced by combining address information and commands such as an active signal, a write signal, a read signal, and a mode register set signal and are used for controlling the driving of the specific blocks.
Meanwhile, unnecessary power consumption occurs in generating the internal driving control signals INT_ACT<0:7>, INT_WT<0:7>, INT_RD<0:7> and MRS. The necessary power is consumed because the address decoder 16 and the address command combiner 18 are driven even though commands requiring no address information are inputted.
Further, power consumption caused by the unnecessary driving greatly occurs in the mobile semiconductor memory device because of long lines on a chip layout for the internal addresses INT_ADD1, INT_ADD2 and INT_ADD3. For these reasons, many efforts have been made to reduce the power consumption. An internal control signal generating circuit for the mobile semiconductor memory device will be described below with reference to FIGS. 2 and 3.
FIG. 2 is a block diagram of an internal control signal generating circuit for a typical mobile semiconductor memory device.
Referring to FIG. 2, the typical mobile semiconductor memory device includes first to third address buffers 32, first to third address latches 34, an output controller 36, first to fourth command buffers 42, first to fourth command latches 44, a command decoder 46, an output control signal generator 50, an address decoder 60 and an address command combiner 70.
The first to third address buffers 32 receive addresses ADD1, ADD2 and ADD3 respectively. The first to third address latches 34 latch output signals of the first to third address buffers 32 in response to an internal clock CLK, respectively. The first to fourth command buffers 42 receive external commands /RAS, /CAS, /WE and /CS respectively. The first to fourth command latches 44 latch output signals of the command buffers 42 in response to the internal clock CLK and output internal commands /RAS_1, /CAS_1, /WE_1 and /CS_1, respectively. The command decoder 46 receives the internal commands /RAS_1, /CAS_1, /WE_1 and /CS_1 to output pre-control signals PRE_ACT, PRE_WT, PRE_RD and PRE_MRS, and the output control signal generator 50 receives the pre-control signals PRE_ACT, PRE_WT, PRE_RD and PRE_MRS to generate an output control signal AGC. The output controller 36 receives output signals of the first to third address latches 34 and transfers internal addresses INT_ADD1, INT_ADD2 and INT_ADD3 in response to the output control signal AGC. The address decoder 60 decodes the internal addresses INT_ADD1, INT_ADD2 and INT_ADD3 to output address information signals ADD_INFO<0:N>, N being a positive integer, and the address command combiner 70 combines the address information signals ADD_INFO<0:N> and the pre-control signals PRE_ACT, PRE_WT, PRE_RD and PRE_MRS to output a plurality of internal driving control signals INT_ACT<0:7>, INT_WT<0:7>, INT_RD<0:7> and MRS having address information.
FIG. 3 is a circuit diagram of the command decoder 46 illustrated in FIG. 2.
Referring to FIG. 3, the command decoder 46 includes a signal input unit 46A, a signal transfer unit 46B, and a latch unit 46C.
The signal input unit 46A is configured to receive the internal commands /RAS_1, /CAS_1, /WE_1 and /CS_1. The signal transfer unit 46B is configured to invert an output signal of the signal input unit 46A in response to the internal clock CLK of a logic low level. The latch unit 46C is configured to latch an output signal of the signal transfer unit 46B in response to the internal clock CLK of a logic high level and output the pre-control signal PRE_ACT.
In the command decoder 46, only a block for generating the pre-control signal PRE_ACT is illustrated in FIG. 3. Although not shown in FIG. 3, decoding blocks for generating the pre-control signals PRE_WT, PRE_RD and PRE_MRS are separately provided in the command decoder 46.
An operation of the command decoder 46 will be described below.
The signal input unit 46A activates the output signal to a logic high level when the internal commands /RAS_1, /CAS_1, /WE_1 and /CS_1 are activated to a logic high level. The signal transfer unit 46B transfers the output signal of the signal input unit 46A to the latch unit 46C while the internal clock CLK is a logic low level, and the latch unit 46C latches and outputs the pre-control signal PRE_ACT in response to the internal clock CLK of a logic high level.
An operation of the mobile semiconductor memory device will be described below.
The external commands /RAS, /CAS, /WE and /CS and the addresses ADD1, ADD2 and ADD3 are inputted.
The first to third address buffers 32 receive the addresses ADD1, ADD2 and ADD3 and convert them into internal voltage levels, and the first to third address latches 34 latch the output signals of the first to third address buffers 32 in synchronization with a rising edge of the internal clock CLK.
The first to fourth command buffers 42 receive the external commands /RAS, /CAS, /WE and /CS and convert them into internal voltage levels, and the first to fourth command latches 44 latch the output signals of the first to fourth command buffers 42 while the internal clock CLK is a logic low level, and output the internal commands /RAS_1, /CAS_1, /WE_1 and /CS_1. The command decoder 46 decodes the internal commands /RAS_1, /CAS_1, /WE_1 and /CS_1 and outputs the pre-control signals PRE_ACT, PRE_WT, PRE_RD and PRE_MRS while the internal clock CLK is a logic high level.
The output control signal generator 50 activates the output control signal AGC when one of the pre-control signals PRE_ACT, PRE_WT, PRE_RD and PRE_MRS is activated.
The output controller 36 outputs the outputs of the first to fourth command latches 44 as the internal addresses INT_ADD1, INT_ADD2 and INT_ADD3 in response to the output control signal AGC.
The address decoder 60 decodes the internal addresses INT_ADD1, INT_ADD2 and INT_ADD3 to output the plurality of address information signals ADD_INFO<0:N>.
The address command combiner 70 combines the pre-control signals PRE_ACT, PRE_WT, PRE_RD and PRE_MRS and the address information signals ADD_INFO<0:N> to output the internal driving control signals INT_ACT<0:7>, INT_WT<0:7>, INT_RD<0:7> and MRS having the address information.
As described above, the mobile semiconductor memory device further includes the output control signal generator 50 and the output controller 36 for controlling the output of the internal addresses INT_ADD1, INT_ADD2 and INT_ADD3 in response to the activation of one of the pre-control signals PRE_ACT, PRE_WT, PRE_RD and PRE_MRS. The mobile semiconductor memory device of FIG. 2 differs from the SDRAM of FIG. 1 in that the internal addresses INT_ADD1, INT_ADD2 and INT_ADD3 are not toggled during a no-operation (NOP) section or a deselect-command (DSEL) section. Consequently, unnecessary power consumption can be prevented.
In using the mobile semiconductor memory device, a predetermined delay occurs until the internal addresses INT_ADD1, INT_ADD2 and INT_ADD3 and the pre-control signals PRE_ACT, PRE_WT, PRE_RD and PRE_MRS are ensured, thereby leading to decrease in the driving speed of the device. In other words, the output controller 36 and the output control signal generator 50 transfer the internal addresses INT_ADD1, INT_ADD2 and INT_ADD3 when one of the pre-control signals PRE_ACT, PRE_WT, PRE_RD and PRE_MRS is activated. In such a state that the pre-control signals PRE_ACT, PRE_WT, PRE_RD and PRE_MRS have been already applied to the address command combiner 70, the internal addresses INT_ADD1, INT_ADD2 and INT_ADD3 are applied to the address command combiner 70 through the output controller 36 and the address decoder 60. That is, the internal driving control signals INT_ACT<0:7>, INT_WT<0:7>, INT_RD<0:7> and MRS are not generated at a time point when the pre-control signals PRE_ACT, PRE_WT, PRE_RD and PRE_MRS are applied, but a predetermined delay occurs until the internal addresses INT_ADD1, INT_ADD2 and INT_ADD3 are applied. Due to this delay, the operating speed of the mobile semiconductor memory device is relatively slower than that of the general DRAM. On the other hand, recently, in mobile semiconductor memory devices, high speed is considered as important as low power consumption.